1. Technical Field
The present invention generally relates to a method of etching a sacrificial layer and, particularly to a method of etching a sacrificial layer adapted for integrated circuit (IC) processes.
2. Description of the Related Art
In the fabrication technology of integrated circuits, a high dielectric constant (high-K) dielectric layer /metal gate (also abbreviated as HK/MG) technology has been widely adopted, such HK/MG technology would facilitate the manufacturers to lower the leakage current of devices, so that the performance of ICs can be continuously improved. Nowadays, there are two types of parallel HK/MG integration solutions of gate-first process and gate-last process. At the aspect of the gate-first process, the HK/MG structure is formed before the formation of the gate; while at the aspect of the gate-last process, the metal gate is formed after a dummy poly-gate is removed.
In a conventional gate-last process, the removal of dummy poly-gate primarily is carried out by a dry etching process, however, a plasma used in the dry etching process would easily damage a barrier layer of titanium nitride formed above the high-K dielectric layer, so that the finished device encounters the issue of excessive high leakage current. Accordingly, a purpose of the present invention is to solve the drawbacks associated with the prior art.